Is it possible to connect a disk or tape drive directly to the DSP56001 without using a host processor?

The Small Computer Systems Interface (SCSI) should connect as a memory-mapped
device with very little control logic and will connect directly to a variety 
of winchester disk drives and tape drives.  The diagram below shows a possible 
solution using the NCR 53C90 SCSI interface chip and a DSP56001 configuration 
using internal memory only.  Using external memory is possible but additional 
decode logic is necessary.

+------------+                       +------------+         
|            |                       |            |
| DSP56001   |                       | NCR 53C90  |
|            |           4           |            |
|      A0-A3 |-----------/-----------| A0-A3      |
|            |                       |            |
|            |           8           |            |
|      D0-D7 |-----------/-----------| DB0-DB7    |
|            |     ____              |            |
|            |     \   \             |            |
|        ~DS |---+--|OR \------------| CSN        |     
|       X/~Y |-+-(--|   /            |            |      \
|            | | | /___/             |            |-------\
|            | | +------+     |\     |            |TO SCSI >
|        ~RD |-(--------(-----| >----| RDN        |-------/
|            | +------+ |     |/|\   |            |BUS   /
|        ~WR |--------(-(-------| >--| WRN        |
|            |        | | |\    |/   |            |
|            |        | +-|  o-+     |            |
|            |   /|   |   |/   |     |            |
|      ~IRQB |-o  |-+-(--------(-----| REQ        |
|            |   \| | |  +-----+     |            |
|            |      | |  |  _____    |            |
|            |      | |  |  |    \   |            |
|            |      | |  +--|     \  |            |
|            |      | +-----| NAND o-| ACKN       |
|            |      +-------|     /  |            |
|            |              |____/   |            |
|      ~IRQA |-----------------------| INTN       |
|            |                       |            |
+------------+                       +------------+

Additional information:

1.  The OR gate sourcing CSN is a 74LS32 (the 'LS32 was chosen partly to
    satisfy timing requirements).

2.  The non-inverting buffers sourcing WRN and RDN D flip flop
    are two of the other three gates in the 74LS32 package.  They
    are used to delay ~WR and ~RD to meet timing requirements.

3.  The three input NAND is a 74ALS10.  The combined delay of the
    three input NAND and the inverter sourcing it should be the same
    as the 74LS32.

4.  The two inverters are the other two gates in the 74ALS10.

5.  INTN needs a pull up resistor.  

6.  One wait state should be used to meet timing requirements.

7.  If additional external memory is used, ~DS should be gated with
    additional address lines (A4 TO A15).  Additional address decode 
    logic must have a delay of less than 17ns to avoid needing an extra 
    memory access wait state.  

8.  The ~IRQA and ~IRQB signals can be either edge sensitive or level
    sensitive.  

9.  The timing requires that the read and write software loops be at 
    least two instructions which will give a data rate of 4.5 million 
    bytes per second (faster than most SCSI devices).

10. The SCSI registers are mapped into the Y memory and the DMA data
    transfers are mapped into the X memory.

