 +---------------------------------------------------------------------+
 |   Question: Can multi-channel adaptive filtering be done with the   |
 |             DSP56200?   A multi-channel  adaptive filter has more   |
 |             than   one reference signal,   each  of which  passes   |
 |             through an FIR filtering structure.                     |
 +---------------------------------------------------------------------+

       Answer:
            Yes, the DSP56200 can perform this type  of  filtering.
       The  DSP56200 uses its DATA RAM ACCESS register to provide a
       third input for this filter, as  shown  in  Figure  1.   The
       number  of  taps  in each filter is programmable by the user
       and depends on the values in the FIR TAP LENGTH  and  RAMADR
       registers.





          d(n)  -----------------------------------
                                                 + |
                                                   v
                               -------------  -   ---
         x1(n)  -------------->|  1st FIR  |---->| + |---+---> Error
                               | Structure |      ---    |     Term
                               -------------       ^     |
                                     ^           - |     |
                                     |             |     |
                    -------    -------------       |     |
       D-RAM(n) --->|  -1 |--->|  2nd FIR  |-------      |
                    | z   |    | Structure |             |
                    -------    -------------             |
                                     ^                   |
                                     |                   |
                                      -------------------

                Figure 1. Multiple-Reference Adaptive Filter

       Configuring the DSP56200 as a Multi-Channel Adaptive Filter:

       1.   The DSP56200's FIR TAP LENGTH register must  be  loaded
            with  the  sum of the number of taps in each of the two
            FIR structures.  This  is  different  than  the  normal
            operating  modes of the DSP56200, where the register is
            loaded with the number of taps minus one.  The  sum  of
            the  number  of  taps must be less than or equal to 255
            and must be greater than or equal to 4 taps.  Note that
            the  number  of  taps  in the 1st FIR structure doesn't
            have to equal the number of taps in the 2nd FIR  struc-
            ture.

       2.   The DSP56200's  CONFIGURATION  register  must  be  pro-
            grammed  as  a  Single  Adaptive FIR Filter (Bits 6,7).
            The rounding, coefficient update disable,  and  leakage
            features  work  in  the  same  manner as for a standard
            adaptive filter.  The DC Tap option, however,  is  only
            available  to  the 2nd FIR structure, and is controlled
            with the DC Tap Enable bit.

       3.   In addition to writing the X1 and D registers, the host
            processor  must also write the RAMADR, DATA and COEFFI-
            CIENT RAM ACCESS registers every  sample  period.   All
            three bytes of the COEFFICIENT RAM ACCESS register must
            be written with zeros.  The DATA RAM ACCESS register is
            written with a 16-bit input data sample for the 2nd FIR
            structure, and the RAMADR is written with the number of
            taps  in  the  1st FIR structure.  Once the DSP56200 is
            initialized, it is important to write ALL these  regis-
            ters  every  sample period.  Also note that there is an
            internal delay of one sample  period  on  the  2nd  FIR
            structure's input stream.

       4.   Unused Data  and  Coefficient  RAM  locations  are  not
            available  to the user during real time operation since
            the DATA and COEFFICIENT RAM ACCESS registers  must  be
            written every sample period.

       5.   As in the case of the standard adaptive filtering mode,
            the  DSP56200  provides the 2's complement of the error
            term in the OUTPUT register when operating as a  multi-
            channel adaptive filter.

       6.   Performance is determined using  the  DSP56200  perfor-
            mance  equations  for  the Single Adaptive Filter Mode.
            In these equations,

                 "N = Maximum number of taps used on any chip"
                         must be replaced with
                "N = Value of the FIR TAP LENGTH register + 1"


       Design Example:

            Determine the values written to the DSP56200  registers
       in the 2-channel adaptive filter shown in Figure 2:

          d(n)  ----------------------------------
                                                + |
                                                  v
                               ------------  -   ---
         x1(n)  -------------->| 1st  FIR |---->| + |---+---> Error
                               | (3 taps) |      ---    |     Term
                               ------------       ^     |
                                     ^          - |     |
                                     |            |     |
                    -------    ------------       |     |
       D-RAM(n) --->|  -1 |--->| 2nd  FIR |-------      |
                    | z   |    | (8 taps) |             |
                    -------    ------------             |
                                     ^                  |
                                     |                  |
                                      ------------------

          Figure 2. Design Example, 2-Channel Adaptive Filter

       The register values are calculated below for both  the  ini-
       tialization  and  real  time  filtering phases of operation.
       During real time filtering, each  of  these  five  registers
       must  be  written  every sampling period.  The values of all
       other registers and of the don't care bits are determined by
       the nature of the application.

          Values for DSP56200 Initialization:

             FIR TAP LENGTH = Sum of the number of taps
                            = 3 taps + 8 taps
                            = 11 taps (decimal)
             CONFIGURATION  = 100xxxxx (binary)
                                 ("x" stands for "don't care")

          Values for DSP56200 Realtime Filtering:

             D                = Primary input
             X1               = Reference input (3-tap channel)
             DATA RAM ACCESS  = Reference input (8-tap channel)
             COEFF RAM ACCESS = 0
             RAMADR           = Number of taps in the 1st FIR
                              = 3

          Performance Calculation:

             Performance is determined using equations in the
             DSP56200 Technical Summary, BR283.

                      n = Number of chips cascaded together
                        = 1
                      N = FIR TAP LENGTH + 1
                        = 11 + 1
                        = 12

                #cycles = 17 + 2*N + r
                        = 17 + 2*N + (30 + n - N)
                        = 17 + 2*12 + (30 + 1 - 12)
                        = 60

                Maximum fs = fck / #cycles
                           = 10.25 Mhz / 60
                           = 170 Khz
