patch-2.4.22 linux-2.4.22/include/asm-mips/dec/kn03.h

• Lines: 82
• Date: 2003-08-25 04:44:43.000000000 -0700
• Orig file: linux-2.4.21/include/asm-mips/dec/kn03.h
• Orig date: 2002-11-28 15:53:15.000000000 -0800

diff -urN linux-2.4.21/include/asm-mips/dec/kn03.h linux-2.4.22/include/asm-mips/dec/kn03.h
@@ -10,34 +10,30 @@
  *
  * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
  * are by courtesy of Chris Fraser.
- * Copyright (C) 2000, 2002  Maciej W. Rozycki
- *
- * These are addresses which have to be known early in the boot process.
- * For other addresses refer to tc.h ioasic_addrs.h and friends.
+ * Copyright (C) 2000, 2002, 2003  Maciej W. Rozycki
  */
 #ifndef __ASM_MIPS_DEC_KN03_H
 #define __ASM_MIPS_DEC_KN03_H
 
 #include <asm/addrspace.h>
+#include <asm/dec/ecc.h>
+#include <asm/dec/ioasic_addrs.h>
+
+#define KN03_SLOT_BASE	KSEG1ADDR(0x1f800000)
 
 /*
  * Some port addresses...
  */
-#define KN03_IOASIC_BASE	KSEG1ADDR(0x1f840000)	/* I/O ASIC */
-#define KN03_RTC_BASE		KSEG1ADDR(0x1fa00000)	/* RTC */
-#define KN03_MCR_BASE		KSEG1ADDR(0x1fac0000)	/* MCR */
-
-#define KN03_MCR_BNK32M		(1<<10)			/* 32M stride */
-#define KN03_MCR_ECCEN		(1<<13)			/* ECC enabled */
-
-#define KN03_IOASIC_REG(r)	(KN03_IOASIC_BASE+(r))
+#define KN03_IOASIC_BASE	(KN03_SLOT_BASE + IOASIC_IOCTL)	/* I/O ASIC */
+#define KN03_RTC_BASE		(KN03_SLOT_BASE + IOASIC_TOY)	/* RTC */
+#define KN03_MCR_BASE		(KN03_SLOT_BASE + IOASIC_MCR)	/* MCR */
 
 
 /*
  * CPU interrupt bits.
  */
 #define KN03_CPU_INR_HALT	6	/* HALT button */
-#define KN03_CPU_INR_MEMORY	5	/* memory, I/O bus write errors */
+#define KN03_CPU_INR_BUS	5	/* memory, I/O bus read/write errors */
 #define KN03_CPU_INR_RES_4	4	/* unused */
 #define KN03_CPU_INR_RTC	3	/* DS1287 RTC */
 #define KN03_CPU_INR_CASCADE	2	/* I/O ASIC cascade */
@@ -55,11 +51,33 @@
 #define KN03_IO_INR_LANCE	8	/* LANCE (Am7990) Ethernet */
 #define KN03_IO_INR_SCC1	7	/* SCC (Z85C30) serial #1 */
 #define KN03_IO_INR_SCC0	6	/* SCC (Z85C30) serial #0 */
-#define KN03_IO_INR_RTC		5	/* DS1287 RTC (?) */
+#define KN03_IO_INR_RTC		5	/* DS1287 RTC */
 #define KN03_IO_INR_PSU		4	/* power supply unit warning */
 #define KN03_IO_INR_RES_3	3	/* unused */
-#define KN03_IO_INR_ASC_DATA	2	/* SCSI data ready (discouraged?) (?) */
-#define KN03_IO_INR_PBNC	1	/* HALT button debouncer */
-#define KN03_IO_INR_PBNO	0	/* ~HALT button debouncer */
+#define KN03_IO_INR_ASC_DATA	2	/* SCSI data ready (for PIO) */
+#define KN03_IO_INR_PBNC	1	/* ~HALT button debouncer */
+#define KN03_IO_INR_PBNO	0	/* HALT button debouncer */
+
+
+/*
+ * Memory Control Register bits.
+ */
+#define KN03_MCR_RES_16		(0xffff<<16)	/* unused */
+#define KN03_MCR_DIAGCHK	(1<<15)		/* diagn/norml ECC reads */
+#define KN03_MCR_DIAGGEN	(1<<14)		/* diagn/norml ECC writes */
+#define KN03_MCR_CORRECT	(1<<13)		/* ECC correct/check */
+#define KN03_MCR_RES_11		(0x3<<12)	/* unused */
+#define KN03_MCR_BNK32M		(1<<10)		/* 32M/8M stride */
+#define KN03_MCR_RES_7		(0x7<<7)	/* unused */
+#define KN03_MCR_CHECK		(0x7f<<0)	/* diagnostic check bits */
+
+/*
+ * I/O ASIC System Support Register bits.
+ */
+#define KN03_IO_SSR_TXDIS1	(1<<14)		/* SCC1 transmit disable */
+#define KN03_IO_SSR_TXDIS0	(1<<13)		/* SCC0 transmit disable */
+#define KN03_IO_SSR_RES_12	(1<<12)		/* unused */
+
+#define KN03_IO_SSR_LEDS	(0xff<<0)	/* ~diagnostic LEDs */
 
 #endif /* __ASM_MIPS_DEC_KN03_H */