patch-2.4.22 linux-2.4.22/arch/mips/momentum/ocelot_g/irq.c

• Lines: 41
• Date: 2003-08-25 04:44:40.000000000 -0700
• Orig file: linux-2.4.21/arch/mips/momentum/ocelot_g/irq.c
• Orig date: 2002-11-28 15:53:10.000000000 -0800

diff -urN linux-2.4.21/arch/mips/momentum/ocelot_g/irq.c linux-2.4.22/arch/mips/momentum/ocelot_g/irq.c
@@ -60,18 +60,18 @@
 	/* do the low 8 bits first */
 	clr_mask = 0xff & clr_mask_in;
 	set_mask = 0xff & set_mask_in;
-	status = read_32bit_cp0_register(CP0_STATUS);
+	status = read_c0_status();
 	status &= ~((clr_mask & 0xFF) << 8);
 	status |= (set_mask & 0xFF) << 8;
-	write_32bit_cp0_register(CP0_STATUS, status);
+	write_c0_status(status);
 
 	/* do the high 8 bits */
 	clr_mask = 0xff & (clr_mask_in >> 8);
 	set_mask = 0xff & (set_mask_in >> 8);
-	status = read_32bit_cp0_set1_register(CP0_S1_INTCONTROL);
+	status = read_c0_intcontrol();
 	status &= ~((clr_mask & 0xFF) << 8);
 	status |= (set_mask & 0xFF) << 8;
-	write_32bit_cp0_set1_register(CP0_S1_INTCONTROL, status);
+	write_c0_intrcontrol(status);
 }
 
 static inline void mask_irq(unsigned int irq)
@@ -145,7 +145,7 @@
 	 * Clear all of the interrupts while we change the able around a bit.
 	 * int-handler is not on bootstrap
 	 */
-	clear_cp0_status(ST0_IM | ST0_BEV);
+	clear_c0_status(ST0_IM | ST0_BEV);
 	__cli();
 
 	/* Sets the first-level interrupt dispatcher. */
@@ -161,7 +161,7 @@
 
 	gt64240_irq_init();
 
-#ifdef CONFIG_REMOTE_DEBUG
+#ifdef CONFIG_KGDB
 	printk("start kgdb ...\n");
 	set_debug_traps();
 	breakpoint();	/* you may move this line to whereever you want :-) */